ECE Seminar: Dealing with Complexity in Verification and Test of Integrated Circuits

Advances in semiconductor technology have enabled the integration of many digital cores along with mixed-signal and RF modules on a singlesystem-on-chip (SoC). This offers many benefits in cost and performance, butposes significant challenges for verifying the correctness of the design andfor testing manufactured chips for defects. Verification of the design has todeal with enormous state spaces. Tests for defects in nanometer scaletechnologies have to detect small delay variations, as well as deal withembedded analog and RF modules. This talk will describe techniques fordealing with these problems, including abstractions based on static analysisof the design description, exploiting the hierarchy in the design, reducingthe search space using approximations, and using on-chip circuitry tofacilitate test of embedded modules. Jacob A. Abraham is Professor of Electrical and Computer Engineering andProfessor of Computer Sciences at the University of Texas at Austin. He isalso the director of the Computer Engineering Research Center and holds aCockrell Family Regents Chair in Engineering. He received his Ph.D. in Electrical Engineering and Computer Science from Stanford University in 1974. His research interests include VLSI design, verification, test, faulttolerance and security.