NAIS: neural architecture and implementation search

In this talk, I will introduce a neural network and hardware implementation co-search methodology, named NAIS, to pursue aggregated solutions of high accuracy DNN designs and efficient hardware deployments simultaneously. To enable a comprehensive co-search framework, there are three indispensable components: 1) efficient hardware accelerator design (e.g. FPGA); 2) hardware-aware neural architecture search (NAS); 3) automatic design tools to quickly deploy DNNs to hardware platforms. I will discuss each component and their integrations to support an efficient and optimal NAIS implementation.